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1 6-channel smbus/i 2 c or pwm dimming led driver with phase shift control isl97671a the isl97671a is a 6-channel 45v dual dimming capable led driver that can be used with either smbus/i 2 c or pwm signal for dimming control. the isl97671a can drive six channels of leds from input 4.5v~26.5v to output of up to 45v. it can also operate from input as low as 3v to output of up to 26.5v in bootstrap configuration (see figure 40). the isl97671a features optional channel phase shift control to minimize the input, output ripple characteristics and load transients as well as spreading the light output to help reduce the video and audio interference from the backlight driver operation. the device can also be configur ed in direct pwm dimming with minimum dimming duty cycle of 0.007% at 200hz. the isl97671a can compensate for th e non-uniformity of the forward voltage drops in the led strings and its headroom control circuit monitors the highest led forward volt age string for output regulation, to minimize the voltage headroom and power loss in a typical multi-string operation. the isl97671a is offered in compact and thermally efficient qfn-20 4mmx3mm package. features ?6 x 50ma channels ? 4.5v to 26.5v input with max 45v output ? 3v (see figure 40) to 21v input with max 26.5v output ? pwm dimming with phase shift control ?smbus/i 2 c controlled pwm or dc dimming ? direct pwm dimming ? pwm dimming linearity - pwm dimming with adjustable dimming freq and duty cycle linear from 0.4% to 100% <30khz - direct pwm dimming duty cycl e linear from 0.007% to 100% at 200hz ? current matching 0.7% ? 600khz/1.2mhz selectable switching frequency ? dynamic headroom control ?fault protection - string open/short circuit, ov p, otp, and optional output short circuit fault protection ? 20 ld 4mmx3mm qfn package applications ? tablet pc to notebook displays led backlighting ? lcd monitor led backlighting ? rgb leds or field sequential led backlighting typical application circuits figure 1a. smbus/i 2 c controlled dimming figure 1b. pwm dimming with adjustable dimming figure 1c. direct pwm dimming figure 1. isl97671a typical application diagrams smbdat/sda vin = 4.5~26.5v pwm comp vin ovp rset 45v*, 6 x 50ma vdc smbclk/scl ch0 ch3 ch2 ch4 ch5 fpwm 2 4 7 6 5 17 8 15 14 13 12 11 10 16 18 lx 20 pgnd 19 agnd 9 isl97671a ch1 en 3 *vin > 12v fault 1 q1 (optional) 45v*, 6 x 50ma *vin > 12v smbdat/sda pwm comp vin ovp rset vdc smbclk/scl ch0 ch3 ch2 ch4 ch5 fpwm 2 4 7 6 5 17 8 15 14 13 12 11 10 16 18 lx 20 pgnd 19 agnd 9 isl97671a ch1 en 3 fault q1 (optional) vin = 4.5~26.5v 1 45v*, 6 x 50ma *vin > 12v smbdat/sda pwm comp vin ovp rset vdc smbclk/scl ch0 ch3 ch2 ch4 ch5 fpwm 2 4 7 6 5 17 8 15 14 13 12 11 10 16 18 lx 20 pgnd 19 agnd 9 isl97671a ch1 en 3 fault q1 (optional) vin = 4.5~26.5v 1 march 24, 2011 fn7709.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl97671a 2 fn7709.1 march 24, 2011 block diagram 45v*, 6 x 50ma generator v in comp + - + - ch0 ch5 v in = 4.5v to 26.5v fet driver reg isl97671a ramp comp imax ilimit pwm/oc/sc pwm brightness control device control fault/status identification registers highest vf string detect dc brightness control vdc sensor fpwm led pwm control pgnd configuration + - agnd reference smbclk/scl smbdat/sda gm amp + - + - logic ovp lx osc and s = 0 dc oc, sc detect fault/status register temp fault/status register pwm rset + - oc, sc detect smbus/i 2 c interface en *v in > 12v and pwm control logic fault/status register figure 2. isl97671a block diagram ovp fault
isl97671a 3 fn7709.1 march 24, 2011 pin configuration isl97671a (20 ld qfn) top view ordering information part number (notes 1, 2, 3) part marking package (pb-free) pkg. dwg. # isl97671airz 671a 20 ld 3x4 qfn l20.3x4 ISL97671AIRZ-EVALZ evaluation board notes: 1. add ?-t* suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic pack aged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-fr ee products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl97671a . for more information on msl please see techbrief tb363 . lx pgnd comp rset smbclk/scl fpwm agnd ch0 fault vin en vdc pwm smbdat/sda ovp ch5 ch4 ch3 ch2 ch1 1 2 3 4 5 6 16 15 14 13 12 11 20 19 18 17 78910 pin descriptions (i = input, o = output, s = supply, x = don?t care) pin name pin # type description fault 1 o fault disconnect switch gate control. vin 2 s input voltage for the device and led power. en 3 i the device needs 4ms for initial power-up enable. it will be disabled if it is not biased for longer than 28ms. vdc 4 s de-couple capacitor for internally generated supply rail. pwm 5 i pwm brightness control pin or dpst control input. smbdat/sda* 6 i/o smbus/i 2 c serial data input and output. when pins 6 and 7 are grounded or in logic 0?s for longer than 60ms, the drivers will be controlled by external pwm signal. smbclk/scl* 7 i smbus/i 2 c serial clock input. when pins 6 and 7 are grounded or in logic 0?s for longer than 60ms, the drivers will be controlled by external pwm signal. fpwm 8 i set pwm dimming frequency, fpwm by connecting a resistor. when fpwm ties to vdc and smbclk/smbdat tie to ground, the device will be in direct pwm dimming wh ere the output follows the input frequency and duty cycle without any digitization. agnd 9 s analog ground for precision circuits. ch0, ch1 ch2, ch3 ch4, ch5 10, 11, 12, 13, 14, 15 i input 0, input 1, input 2, input 3, input 4, input 5 to current source, fb, and monitoring. ovp 16 i overvoltage protection input. rset 17 i resistor connection for setting led cu rrent, (see equation 2 for calculating the i led(peak) ). comp 18 o boost compensation pin. pgnd 19 s power ground lx 20 o input to boost switch. epad no electrical connection but should be used to conn ect pgnd and agnd. for example uses top plane as pgnd and bottom plane as agnd with vias on epad to allow heat dissipation and minimum noise coupling from pgnd to agnd operation.
isl97671a 4 fn7709.1 march 24, 2011 table of contents typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . 1 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . 5 thermal information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . 8 theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pwm boost converter . . . . . . . . . . . . . . . . . . . . . . . . . 11 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ovp and v out requirement . . . . . . . . . . . . . . . . . . . . . 11 current matching and current accuracy . . . . . . . . . . . 11 dynamic headroom control . . . . . . . . . . . . . . . . . . . . 11 dimming controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 maximum dc current setting . . . . . . . . . . . . . . . . . 12 pwm dimming control . . . . . . . . . . . . . . . . . . . . . . 12 pwm dimming frequency adjustment . . . . . . . . . . . 12 direct pwm dimming . . . . . . . . . . . . . . . . . . . . . . . . . . 13 phase shift control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5v low dropout regulator . . . . . . . . . . . . . . . . . . . . . . 14 power-up sequencing, soft-start, and fault management . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 in-rush control and soft-start . . . . . . . . . . . . . . . . . . . 14 fault protection and monitoring . . . . . . . . . . . . . . . . . 14 short circuit protection (scp) . . . . . . . . . . . . . . . . . . . 14 open circuit protection (ocp) . . . . . . . . . . . . . . . . . . . 14 overvoltage protection (ovp) . . . . . . . . . . . . . . . . . . . . 15 undervoltage lock-out. . . . . . . . . . . . . . . . . . . . . . . . . . 15 input overcurrent protection . . . . . . . . . . . . . . . . . . . . 15 over-temperature protection (otp). . . . . . . . . . . . . . . 15 smbus/i 2 c communications. . . . . . . . . . . . . . . . . . . . . . . 18 write byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 read byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 slave device address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 smbus/i 2 c register definitions . . . . . . . . . . . . . . . . . 18 pwm brightness control register (0x00). . . . . . . . . . 19 device control register (0x01) . . . . . . . . . . . . . . . . . . . 20 fault/status register (0x02) . . . . . . . . . . . . . . . . . . . . 21 identification register (0x03) . . . . . . . . . . . . . . . . . . . . 21 dc brightness control register (0x07). . . . . . . . . . . . 22 configuration register (0x08) . . . . . . . . . . . . . . . . . . . 22 output channel mask/fault readout register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 phase shift control register (0x0a) . . . . . . . . . . . . . . 24 components selections . . . . . . . . . . . . . . . . . . . . . . . . . . 24 input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 output ripple. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 schottky diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 high current applications . . . . . . . . . . . . . . . . . . . . . . . 25 multiple drivers operation . . . . . . . . . . . . . . . . . . . . . . 25 low voltage operations . . . . . . . . . . . . . . . . . . . . . . . . . 26 16-bit dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 rgb leds or field sequenctial led backlighting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . 28
isl97671a 5 fn7709.1 march 24, 2011 absolute maximum ratings (t a = +25 c) thermal information vin, en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 28v fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vin - 8.5v to vin + 0.3v vdc, comp, rset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 5.5v smbclk/scl * , smbdat/sda * , fpwm, pwm . . . . . . . . . . . . -0.3v to 5.5v en, ovp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 5.5v ch0 - ch5, lx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 45v pgnd, agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v above voltage ratings are all with respect to agnd pin esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 3kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 300v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kv thermal resistance (typical) ja (c/w) jc (c/w) 20 ld qfn package (notes 4, 5, 7) . . . . . . 40 2.5 thermal characterization (typical) psi jt (c/w) 20 ld qfn package (note 6) . . . . . . . . . . . . . . . . . . . . . 1 maximum continuous junction temperature . . . . . . . . . . . . . . . . .+125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. psi jt is the psi junction-to-top thermal characte rization parameter. if the package top temp erature can be measured with this rating then the die junction temperature can be estimated more accurately than the jc and jc thermal resistance ratings. 7. refer to jesd51-7 high effective thermal conducti vity board layout for proper via and plane designs. electrical specifications v in = 12v, en = 5v, r set = 20.1k , unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. parameter description condition min (note 8) typ max (note 8) unit general v in (note 9) backlight supply voltage 13 leds per channel (3.2v/20ma type) 4.5 26.5 v i vin_stby v in shutdown current t a = +25c 5 a i vin v in active current en = 5v 5 ma v out output voltage 4.5v < v in 26v, f sw = 600khz 45 v 8.55v < v in 26v, f sw = 1.2mhz 45 v 4.5v < v in 8.55v, f sw =1.2mhz v in /0.19 v v uvlo undervoltage lockout threshold 2.1 2.6 v v uvlo_hys undervoltage lockout hysteresis 200 mv regulator v dc ldo output voltage v in 6v 4.55 4.8 5 v i vdc_stby standby current en = 0v 5 a v ldo vdc ldo droop voltage v in > 5.5v, 20ma 20 200 mv en low guaranteed range for en input low voltage 0.5 v en hi guaranteed range for en input high voltage 1.8 v t enlow en low time before shut-down 30.5 ms boost sw ilimit boost fet current limit 1.5 2.0 2.7 a
isl97671a 6 fn7709.1 march 24, 2011 r ds(on) internal boost switch on-resistance t a = +25c 235 300 m ss soft-start 100% led duty cycle 7 ms eff_peak peak efficiency v in = 12v, 72 leds, 20ma each, l = 10h with dcr 101m ? , t a = +25c 92.9 % v in = 12v, 60 leds, 20ma each, l = 10h with dcr 101m ? , t a = +25c 90.8 % i out / v in line regulation 0.1 % d max boost maximum duty cycle f sw = 1, 600khz 90 % f sw = 0, 1.2mhz 81 d min boost minimum duty cycle f sw = 1, 600khz 9.5 % f sw = 0, 1.2mhz 17 f osc_hi lx frequency high f sw = 1, 600khz 475 600 640 khz f osc_lo lx frequency low f sw = 0, 1.2mhz 0.97 1.14 1.31 mhz i lx_leakage lx pin leakage current lx = 45v, en = 0v 10 a reference fault detection v sc short circuit threshold accuracy 7.5 8.2 v temp_shtdwn temperature shutdown threshold 150 c temp_hyst temperature shutdown hysteresis 23 c v ovplo overvoltage limit on ovp pin 1.19 1.25 v current sources i match dc channel-to-channel current matching r set = 20.1k , reg0x00 = 0xff, (i out =20ma) 0.7 1.0 % i acc current accuracy -1.5 +1.5 % v headroom dominant channel current source headroom at ch pin i led = 20ma t a = +25c 500 mv v rset voltage at rset pin r set = 20.1k ? 1.2 1.22 1.24 v i led(max) maximum led current per channel v in = 12v, v out = 45v, fsw = 1.2mhz, t a = +25c 50 ma pwm generator v il guaranteed range for pwm input low voltage 0.8 v v ih guaranteed range for pwm input high voltage 1.5 vdd v f pwmi pwm input frequency range 200 30,000 hz pwmacc pwm dimming accuracy (except direct pwm dimming) 8bits t directpwm direct pwm minimum on time direct pwm mode 250 350 ns f pwm pwm dimming frequency range 100 30,000 hz fault pin i fault fault pull-down current v in = 12v 12 21 30 a v fault fault clamp voltage with respect to v in v in = 12, v in - v fault 6 7 8.3 v electrical specifications v in = 12v, en = 5v, r set = 20.1k , unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter description condition min (note 8) typ max (note 8) unit
isl97671a 7 fn7709.1 march 24, 2011 lxstart_thres lx start-up threshold 0.9 1.2 v ilxstart-up lx start-up current 1 3.5 5 ma smbus/i 2 c interface v il guaranteed range for data, clock input low voltage 0.8 v v ih guaranteed range for data, clock input high voltage 1.5 vdd v v ol smbus/i 2 c data line logic low voltage i pullup = 4ma 0.17 v i leak input leakage on smbdata/smbclk measured at 4.8v -10 10 a smbus/i 2 c timing specifications t en -smb/i 2 c minimum time between en high and smbus/i 2 c enabled 1f capacitor on vdc 2 ms pws pulse width suppression on smbclk/smbdat 0.15 0.45 s f smb smbus/i 2 c clock frequency 400 khz t buf bus free time between stop and start condition 1.3 s t hd:sta hold time after (repeated) start condition. after this period, the first clock is generated 0.6 s t su:sta repeated start condition setup time 0.6 s t su:sto stop condition setup time 0.6 s t hd:dat data hold time 300 ns t su:dat data setup time 100 ns t low clock low period 1.3 s t high clock high period 0.6 s t f clock/data fall time 300 ns t r clock/data rise time 300 ns notes: 8. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. 9. at maximum v in of 26.5v, minimum v out is limited 28v. electrical specifications v in = 12v, en = 5v, r set = 20.1k , unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter description condition min (note 8) typ max (note 8) unit
isl97671a 8 fn7709.1 march 24, 2011 typical performance curves figure 3. efficiency vs up to 20ma led current (100% led duty cycle) vs v in figure 4. efficiency vs up to 30ma led current (100% led duty cycle) vs v in figure 5. efficiency vs v in vs switching frequency at 20ma (100% led duty cycle) figure 6. efficiency vs v in vs switching frequency at 30ma (100% led duty cycle) figure 7. efficiency vs v in vs temperature at 20ma (100% led duty cycle) figure 8. channel-to-channel current matching 100 70 80 90 50 30 40 60 0 10 20 0 5 10 15 20 25 efficiency (%) i led(ma) 5v in 12v in 24v in 100 70 80 90 50 30 40 60 0 10 20 0 5 10 15 20 25 efficiency (%) i led(ma) 30 35 6p10s_30ma/channel 5v in 12v in 24v in 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 1.2mhz 580k efficiency (%) v in 0 5 10 15 20 25 efficiency (%) v in 30 1.2mhz 0 20 40 60 80 100 580k 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 +25c -40c 0c +85c efficiency (%) v in 0.40 0.10 0.20 0.30 -0.10 -0.20 0.00 012345 current matching(%) channel 6 -0.30 -0.40 7 21v in 12v in 4.5v in
isl97671a 9 fn7709.1 march 24, 2011 figure 9. current linearity vs low level pwm dimming duty cycle vs v in figure 10. v headroom vs v in at 20ma figure 11. v out ripple voltage, v in = 12v, 6p12s at 20ma/channel figure 12. in-rush and led current at v in = 6v for 6p12s at 20ma/channel figure 13. in-rush and led current at v in = 12v for 6p12s at 20ma/channel figure 14. line regulation with v in change from 6v to 26v, v in = 12v, 6p12s at 20ma/channel typical performance curves (continued) 0 0.2 0.4 0.6 0.8 1.0 1.2 01 4 dc 23 56 current 12 v in 4.5 v in 0.40 0.45 0.50 0.55 0.60 0 5 10 15 20 25 30 v headroom (v) -40c 0c +25c v in (v) 2.00s/div v o = 50mv/div v in = 6v, 6p12s v o = 20v/div 2.00s/div i_v in = 1a/div iled = 20ma/div en v in = 12v, 6p12s v o = 20v/div 2.00s/div i_v in = 1a/div iled = 20ma/div en 6p12s, 20ma/ch v in = 10v/div 10.0ms/div i_v in = 1a/div iled = 20ma/div en
isl97671a 10 fn7709.1 march 24, 2011 figure 15. line regulation with v in change from 26v to 6v for 6p12s at 20ma/channel figure 16. load regulation with i led change from 0% to 100% pwm dimming, v in =12v, 6p12s at 20ma/channel figure 17. load regulation with i led change from 100% to 0% pwm dimming, v in =12v, 6p12s at 20ma/channel figure 18. isl97672a shuts down and stops switching ~30ms after en goes low figure 19. direct pwm dimming minimum dimming linearity typical performance curves (continued) 6p12s, 20ma/ch v in = 10v/div 10.0ms/div i_v in = 1a/div iled = 20ma/div en 6p12s, 20ma/ch v o = 1v/div 10.0ms/div iled = 20ma/div 6p12s, 20ma/ch v o = 1v/div 10.0ms/div iled = 20ma/div 6p12s, 20ma/ch v o = 10v/div 20.0ms/div i_v in = 1a/div iled = 20ma/div en 0.0030 0.0025 0.0020 0.0015 0.0010 0.006 0.007 0.008 0.009 0.010 0.011 0.012 0.013 0.014 pwm dimming duty cycle (%) i led (ma) i led = 20ma f pwm = 200hz no ch caps
isl97671a 11 fn7709.1 march 24, 2011 theory of operation pwm boost converter the current mode pwm boost converter produces the minimal voltage needed to enable the led stack with the highest forward voltage drop to run at the programmed current. the isl97671a employs current mode control boost architecture that has a fast current sense loop and a slow voltage feedback loop. such architecture achieves a fast transient response that is essential for the notebook backlight application where the power can be a series of drained batteries or instantly change to an ac/dc adapter without rendering a noti ceably visual nuisance. the number of leds that can be driven by isl97671a depends on the type of led chosen in the application. the isl97671a is capable of boosting up to 45v and drive 6 channels of leds. enable the en pin is used to enable or disable the isl97671a operation. it is a high voltage pin that can be tied directly to v in up to 26.5v if the system lacks of i/o for enable signal. ovp and v out requirement the overvoltage protection (ovp) pi n has a function of setting the overvoltage trip level as well as limiting the v out regulation range. the isl97671a ovp threshold is set by r upper and r lower as shown in equation 1: v out can only regulate between 64% and 100% of the v out _ ovp such that: allowable v out = 64% to 100% of v out _ ovp for example, if 10 leds are used with the worst case v out of 35v. if r 1 and r 2 are chosen such that the ovp level is set at 40v, then the v out is allowed to operate between 25.6v and 40v. if the requirement is changed to a 6 leds 21v v out application, then the ovp level must be reduced and users should follow v out = (64% ~100%) ovp requirement. otherwise, the headroom control will be disturbed such that the channel voltage can be much higher than expected an d sometimes it can prevent the driver from operating properly. the ratio of the ovp capacitors should be the inverse of the ovp resistors. for example, if r upper /r lower = 33/1, then c upper /c lower = 1/33 with c upper = 100pf and c lower = 3.3nf. current matching and current accuracy each channel of the led current is regulated by the current source circuit, as shown in figure 20. the led peak current is set by translating the r set current to the output with a scaling factor of 401.8/r set . the source terminals of the current source mosfets are designed to run at 500mv to optimize power loss versus accura cy requirements. the sources of errors of the channel-to-channel current matching come from the op amps offset, internal layout, reference, and current source resistors. these parameters are op timized for current matching and absolute current accuracy. on the other hand, the absolute accuracy is additionally determined by the external r set , and therefore, additional tolerance will be contributed by the current setting resistor. a 1% tolerance resistor is therefore recommended. dynamic headroom control the isl97671a features a pr oprietary dynamic headroom control circuit that detects the hi ghest forward voltage string or effectively the lowest voltage from any of the ch0-ch5 pins. when this lowest channel voltage is lower than the short circuit threshold, v sc , such voltage will be used as the feedback signal for the boost regulator. the boost makes the output to the correct level such that the lowest channe l pin is at the target headroom voltage. since all led stacks ar e connected to the same output voltage, the other channel pins will have a higher voltage, but the regulated current source circuit on each channel will ensure that each channel has the same programmed current. the output voltage will regulate cycle-by-cycle and is always referenced to the highest forward voltage string in the architecture. dimming controls the isl97671a provides smbus/i 2 c controlled pwm or dc dimming where the users need to turn the leds on through the smbus/i 2 c communications (see the ?smbus/i 2 c communications? on page 18). the isl97671a also provides pwm dimming by external pwm signal where the smbclk and smbdat pins are grounded or pulled low and the dimming frequency can be adjusted. the isl97671a also allows direct pwm dimming where the output duty cycle and dimming frequency follow the input pwm signal. the three dimming mode selection is summarized in table 1. v out_ovp 1.21v r upper r lower + () r lower ? = (eq. 1) table 1. dimming mode selection smbclk/scl pin signal smbdat/sda pin signal fpwm pin dimming mode selection low low resistor to ground pwm dimming with adjustable dimming frequency, phase shift enabled low low tie to vdc direct pwm dimming smbus clock smbus data resistor to ground smbus controlled dimming i 2 c clock i 2 c data resistor to ground i 2 c controlled dimming figure 20. simplified current source circuit ref + - + - pwm dimming rset + dc dimming ref + - + - rset -
isl97671a 12 fn7709.1 march 24, 2011 the isl97671a allows two ways of controlling the led current, and therefore, the brightness. they are: 1. dc current adjustment 2. pwm chopping of the led current defined in step 1. there are various ways to achieve dc or pwm current control, described in the following. maximum dc current setting the initial brightness should be set by choosing an appropriate value for r set . this should be chosen to fix the maximum possible led current: once r set is fixed, the led dc current can be adjusted through register 0x07 (brtdc) as follows: brtdc can be programmed from 0 to 255 in decimal and defaults to 255 (0xff). if left at the default value, led current will be fixed at i ledmax . brtdc can be adjusted dynamically on the fly during operation. brtdc = 0 disconnects all channels. for example, if the maximum required led current (i led(max) ) is 20ma, rearranging equation 2 yields equation 4: if brtdc is set to 200 then: pwm dimming control the isl97671a provides multiple pwm dimming methods, as described in the following. each of these methods results in pwm chopping of the current in the le ds for all 6 channels to provide an average led current. during the on periods, the led current will be defined by the value of r set and brtdc, as described in equations 2 and 3. the source of the pwm signal can be described as follows: 1. internally generated 256 step duty cycle programmed through the smbus/i 2 c. 2. external signal from pwm. 3. dpst mode. internally generated signal with a duty cycle defined by the product of the external pwm and smbus/i 2 c programmed pwm at the internal setting frequency. the default pwm dimming is in dpst mode. in all of the methods, the average led channel current is controlled by i led and the pwm duty cycle in percent, as shown in equation 6: method 1 (internal mode, smbus/i 2 c controlled pwm) the average led channel current is controlled by the internally generated pwm signal, as shown in equation 7: where brt is the pwm brightness level programmed in the register 0x00. brt ranges from 0 to 255 in decimal and defaults to 255 (0xff). brt = 0 di sconnects all channels. to use only the smbus/i 2 c controlled pwm brightness control, users need to set register 0x01 to 0x05. the pwm dimming frequency is adjusted by a resistor at the fpwm pin. method 2 (external mode) the average led channel current ca n also be controlled by an external pwm signal, as shown in equation 8: the pwm dimming frequency can be set or applied up to 30khz with duty cycles from 0.4% to 100%. the pwm dimming off time cannot be longer than 28ms or else the driver will enter shutdown. to use externally applied pwm signal only for brightness control, users need to set register 0x01 to 0x03. method 3 (dpst mode) the average led channel current can also be controlled by the product of the smbus/i 2 c controlled pwm and the external pwm signals as: where: therefore: where brt is the value held in register 0x00 (default setting 0xff) controlled by smbus/i 2 c and pwm is the duty cycle of the incoming pwm signal. in this way, the users can change the pwm current in ratiometric manner to achieve dpst compliance backlight dimming. to use the dpst mode, users need to set register 0x01 to 0x01 with an external pwm signal. the dpst mode pwm dimming freque ncy is adjusted by a resistor at the fpwm pin. for example, if the smbus/i 2 c controlled pwm duty is 80% dimming at 200hz (see equation 12) and the external pwm duty cycle is 60% dimming at 1khz, the resultant pwm duty cycle is 48% dimming at 200hz. pwm dimming frequency adjustment the pwm dimming frequency is set by an external resistor at the fpwm pin as: where f pwm is the desirable pwm dimming frequency and r fpwm is the setting resistor. the pwm dimming frequency can be set or applied up to 30khz with duty cycle from 0.4% to 100%. i ledmax 401.8 r set --------------- = (eq. 2) i led 1.58x brtdc r set ? () = (eq. 3) r set 401.8 0.02 ? 20.1k == (eq. 4) i led 1.58 200 20100 15.7ma = ? ? = (eq. 5) i led ave () i led pwm = (eq. 6) i led ave () i led brt 255 ? () = (eq. 7) l iled ave () i led pwmi = (eq. 8) i led ave () i led xpwm dpst = (eq. 9) pwm dpst brt 255 ? pwmi = (eq. 10) i led ave () i led brt 255 ? pwmi = (eq. 11) f pwm 6.66 7 10 rfpwm ------------------------ = (eq. 12)
isl97671a 13 fn7709.1 march 24, 2011 direct pwm dimming when direct pwm dimming mode is selected where f pwm is tied to v dc and smbclk/smbdat are grounded, 6 channels of pwm current will follow the incoming pwm signal?s frequency and duty cycle. the change is analog fashion without any digitization that the minimum duty cycle can be as low as 0.007% at 200hz (or equivalent pulse width of 350ns). to achieve this ultra low duty cycle dimming performance, any channel capacitor, either it is tied to v out or ground, cannot be used. also in direct pwm dimming mode the phase shift function will be disabled. phase shift control the isl97671a is capable of delaying the phase of each current source to minimize load transients . by default, phase shifting is disabled as shown in figure 21 where the channels pwm currents are switching uniformly. the duty cycles can be controlled by the data in pwm br ightness control register via the smbus/i 2 c interface, an external pwm signal with the frequency set by the rf pwm , or by an external pwm signal with the frequency set by the incoming signal. when equalphase = 1, the phase sh ift evenly spreads the channels switching across the pwm cycle, depending on how many channels are enabled, as shown in figures 22 and 23. equal phase means there are fixed delays between channels and such delay can be calculated as equations 13 and 14. where (255/n) is rounded down to the nearest integer. for example, if n = 6, (255/n) = 42, that leads to: t d1 = t fpwm x 42/255 t d2 = t fpwm x 45/255 where t fpwm is the sum of t on and t off . n is the number of led channels. the isl97671a will detect the numbers of operating channels automatically. the isl97671a allows the user to program the amount of phase shift degree in 7-bit resolution, as shown in figure 24. to enable programmable phase shifting, the user must write to the phase shift control register with equalphase = 0 and the desirable phase shift value of phaseshift[6:0]. the delay between ch5 and the repeated ch0 is the rest of the pwm cycle. switching frequency the default switching frequency is 600khz but it can be selected to 600khz or 1.2mhz if the smbus/i 2 c communications is used. the switching frequency select bi t is accessible in the smbus/i 2 c configuration register 0x08 bit 2. figure 21. no delay (default phase shift disabled) iled0 iled1 iled2 iled3 iled4 iled5 t on t off t fpwm t d1 t fpwm 255 ----------------- - x 255 n ---------- ?? ?? = (eq. 13) t d2 t fpwm 255 ----------------- - x 255 n 1 ? () 255 n ---------- ?? ?? ? ?? ?? = (eq. 14) figure 22. 6 equal phase channels phase shift illustration iled0 iled1 iled2 iled3 iled4 iled5 iled0 t on t off pwmi 60% 40% t fpwm 60% 40% t d1 t d1 t d1 t d1 t d1 t d2 figure 23. 4 equal phase channels phase shift illustration iled1 iled2 iled3 iled4 iled1 t on t off pwmi 60 % 4 0% 60% 40% t d1 t d1 t d1 t d2 t fp w m (t pw m out ) t pwmin t d1 = fixed delay with integer only while the decimal value will be discarded (eg. 63.75=63) figure 24. phase shift with 7-bit programmable delay iled0 iled1 iled2 iled3 iled4 iled5 t pd t pd t pd t pd t pd t on t off t fpwm
isl97671a 14 fn7709.1 march 24, 2011 5v low dropout regulator a 5v ldo regulator is present at the vdc pin to develop the necessary low voltage supply, which is used by the chips internal control circuitry. because vdc is an ldo pin, it requires a bypass capacitor of 1f or more for the regulation. low input voltage also allows only lower output voltag e applications only with the maximum boost ratio defined in ?components selections? on page 24. the vdc pin can be used as a coarse reference with a few ma sourcing capability. power-up sequencing, soft-start, and fault management the isl97671a includes circuits to manage input current draw during normal startup, to reduce inrush current as various bulk capacitors charge up. the isl97671a also detects several external fault conditions, and acts to limit fault energy and prevent continued startup while detected faults exist. an external high-side pfet can optionally be fitted in series with vin. the isl97671a turns this fault protection pfet off in the event of a short fault to ground in the boost converter, avoiding damage to the system's main power supply in such an overload condition. in-rush control and soft-start the isl97671a has separately built in independent in-rush control and soft-start functions. the in-rush control function is built around the short circuit protection fet, and is only available in applications, which include this device. at start-up, the fault protection fet is turned on slowly due to a 30a pull-down cu rrent output from the fault pin. this discharges the fault fet's ga te-source capacitance, turning on the fet in a controlled fashion. as this happens, the output capacitor is charged slowly through the weakly turned on fet before it becomes fully enhanced. this results in a lo w in-rush current. this current can be further reduced by adding a ca pacitor (in the 1nf to 5nf range) across the gate-source terminals of the fet. once the boost is enabled the current in the boost power switch is monitored and the switching is terminated in any cycle where the current exceeds the current limit. the isl97671a includes a soft-start feature where this current limit starts at a low value (285ma). this is stepped up to th e final 2.0a current limit in 7 further steps of 285ma. these steps will happen over at least 8ms, and will be extended at low led pwm frequencies if the led duty cycle is low. this allows the output capacitor to be charged to the required value at a low current limit and prevents high input current for systems that have only a low to medium output current requirement. for systems with no master fault protection fet, the in-rush current will flow towards c out when v in is applied and it is determined by the ramp rate of v in and the values of c out and l. fault protection and monitoring the isl97671a features extensive protection functions to cover all the perceivable failure conditions. the failure mode of a led can be either open circuit or as a short. the behavior of an open circuited led can additionally take the form of either infinite resistance or, for some leds, a ze ner diode, which is integrated into the device in parallel with the now opened led. for basic leds (which do not have built-in zener diodes), an open circuit failure of an led will only result in the loss of one channel of leds without affecting other channels. similarly, a short circuit condition on a channel that result s in that channel being turned off does not affect other channels unless a similar fault is occurring. all led faults are reported via the smbus/i 2 c interface to register 0x02 (fault/status register). the controller is able to determine which channels have failed via register 0x09 (output masking register). the controller can also choose to use register 0x09 to disable faulty channels at start-up, resulting in only further faulty channels bein g reported by register 0x02. due to the lag in boost response to any load change at its output, certain transient events (such as led current steps or significant step changes in led duty cycle) can transiently look like led fault modes. the isl97671a uses feedback from the leds to determine when it is in a stable operating region and prevents apparent faults during these transient events from allowing any of the led stacks to fault out. see table 2 on page 16 for more details. a fault condition that results in an input current that exceeds the devices electrical limits will result in a shutdown of all output channels. the control device logic will remain functional such that the fault/status register can be interrogated by the system. the root cause of the failure will be loaded to the volatile fault/status register so that the host processor can interrogate the data for failure monitoring. short circuit protection (scp) the short circuit detection circuit monitors the voltage on each channel and disables faulty channels which are detected above the programmed short circuit threshold. the short circuit threshold is 7.2v minimum. when an led becomes shorted, the action taken is described in table 2. the default short circuit threshold is 7.2v. the detection of this failure mode can be disabled via register 0x08, see table 3b for additional information. open circuit protection (ocp) when one of the leds becomes open circuit, it can behave as either an infinite resistance or a gradually increasing finite resistance. the isl97671a monitors the current in each channel such that any string which reaches the intended output current is considered ?good?. should the cu rrent subsequently fall below the target, the channel will be considered an ?open circuit?. furthermore, should the boost ou tput of the isl97671a reaches the ovp limit or should the lowe r over-temperature threshold be reached, all channels which are not ?good? will immediately be considered as ?open circuit?. de tection of an ?open circuit? channel will result in a time-out before disabling of the affected channel. this time-out is sped up when the device is above the lower over-temperature threshold in an attempt to prevent the upper over-temperature trip point from being reached. some users employ some special types of leds that have zener diode structure in parallel with the led for esd enhancement, thus enabling open circuit operation. wh en this type of led goes open circuit, the effect is as if the led forward voltage has increased, but no lighting. any affected string will not be disabled, unless the failure results in the boost ovp limit being reached, allowing all other leds in the string to remain functional. care should be taken in this case that the boost ovp limit and scp limit are set properly, so as to make sure that multiple failures on one string do not
isl97671a 15 fn7709.1 march 24, 2011 cause all other good channels to be faulted out. this is due to the increased forward voltage of the faulty channel making all other channel look as if they have led shorts. see table 2 for details for responses to fault conditions. overvoltage protection (ovp) the integrated ovp circuit monitors the output voltage and keeps the voltage at a safe level. the ovp threshold is set as: these resistors should be large to minimize the power loss. for example, a 1mk r upper and 30k r lower sets ovp to 41.2v. large ovp resistors also allow c out discharges slowly during the pwm off time. parallel capacitors should also be placed across the ovp resistors such that r upper /r lower = c lower /c upper . using a c upper value of at least 30pf is recommended. these capacitors reduce the ac impeda nce of the ovp node, which is important when using high value resistors. undervoltage lock-out if the input voltage falls below the uvlo level of 2.45v, the device will stop switching and be reset. operation will restart only if the device is re-enabled through smbus/i 2 c interface once the input voltage is back in the normal v in and operating range. in non-smbus/i 2 c applications, the part will automatically restart once the input voltage clears the uvlo threshold with the part already enabled. input overcurrent protection during normal switching operation, the current through the internal boost power fet is monitored. if the current exceeds the current limit, the internal swit ch will be turned off. this monitoring happens on a cycle by cycle basis in a self protecting way. additionally, the isl97671a monitors the voltage at the lx and ovp pins. at start-up, a fixed current is injected out of the lx pins and into the output capacitor. the device will not start up unless the voltage at lx exceeds 1.2v. the ovp pin is also monitored such that if it rises above and subsequently falls below 20% of the target ovp level, the input protection fet will also be switched off. over-temperature protection (otp) the isl97671a includes two over-temperature thresholds. the lower threshold is set to +130c. when this threshold is reached, any channel which is outputting current at a level significantly below the regulation target will be treated as ?open circuit? and disabled after a time-out period. this time-out period is also reduced to 800s when it is above the lower threshold. the intention of the lower threshold is to allow bad channels to be isolated and disabled before they cause enough power dissipation (as a result of other channels having large voltages across them) to hit the upper temperature threshold. the upper threshold is set to +150c. each time this is reached, the boost will stop switching and the output current sources will be switched off. once the device has cooled to approximately +100c, the device will restart with the dc led current level reduced to 75% of the initial setting. if the dissipation problem persists, subsequent hitting of the limit will cause identical behavior, with the current reduced in steps to 50% and finally 25%. hitting of the upper threshold will also set the thermal fault bit of the fault/status register 0x02. unless disabled via the en pin, the device stays in an active state throughout, allows the external processor to interrogate the fault condition. for the extensive fault protection conditions, please refer to figure 25 and table 2 for details. ovp 1.21v r upper r lower + () r lower ? = (eq. 15)
isl97671a 16 fn7709.1 march 24, 2011 figure 25. simplified fault protections q5 vsc ch5 vset dc current pwm/oc0/sc0 ref fet driver fault imax ilimit ovp v in t2 otp thrm shdn q0 vsc ch0 v out smbus/i 2 c control logic fault/ status register vset pwm/oc5/sc5 temp sensor logic lx t1 otp thrm shdn o/p short + - + - reg vset/2 driver table 2. protections table case failure mode detection mode failed channel action good channels action v out regulated by 1 ch0 short circuit upper over-temperature protection limit (otp) not triggered and ch0 < 7.5v ch0 on and burns power. ch1 through ch5 normal highest vf of ch1 through ch5 2 ch0 short circuit upper otp triggered but vch0 < 7.5v all channels go off until chip cooled and then comes back on with current reduced to 76%. subsequent otp triggers will reduce i out further. same as ch0 highest vf of ch1 through ch5 3 ch0 short circuit upper otp not triggered but ch0 > 7.5v ch1 disabled after 6 pwm cycle time-out. ch1 through ch5 normal highest vf of ch1 through ch5 4ch0 open circuit with infinite resistance upper otp not triggered and ch0 < 7.5v v out will ramp to ovp. ch1 will time- out after 6 pwm cycles and switch off. v out will drop to normal level. ch1 through ch5 normal highest vf of ch1 through ch5 5ch0 led open circuit but has paralleled zener upper otp not triggered and ch0 < 7.5v ch1 remains on and has highest vf, thus v out increases. ch1 through ch5 on, q1 through q5 burn power vf of ch0 6ch0 led open circuit but has paralleled zener upper otp triggered but ch0 < 7.5v all channels go off until chip cooled and then comes back on with current reduced to 76%. subsequent otp triggers will reduce i out further same as ch0 vf of ch0 7ch0 led open circuit but has paralleled zener upper otp not triggered but chx > 7.5v ch0 remains on and has highest vf, thus v out increases. v out increases, then ch-x switches off after 6 pwm cycles. this is an unwanted shut off and can be prevented by setting ovp at an appropriate level. vf of ch0 8 channel-to-channel vf too high lower otp triggered but chx < 7.5v any channel at below the target current will fault out after 6 pwm cycles. remaining channels driven with normal current. highest vf of ch0 through ch5
isl97671a 17 fn7709.1 march 24, 2011 9 channel-to-channel vf too high upper otp triggered but chx < 7.5v all channels go off until chip cooled and then comes back on with current reduced to 76%. subsequent otp triggers will reduce i out further highest vf of ch0 through ch5 10 output led stack voltage too high v out > vovp any channel that is below the target current will time-out after 6 pwm cycles, and v out will return to the normal regulation voltage required for other channels. highest vf of ch0 through ch5 11 v out /lx shorted to gnd at start-up or v out shorted in operation lx current and timing are monitored. ovp pins monitored for excursions below 20% of ovp threshold. the chip is permanently shutdown 31ms after power-up if v out /lx is shorted to gnd. table 2. protections table (continued) case failure mode detection mode failed channel action good channels action v out regulated by figure 26. smbus/i 2 c interface v ih v il v ih v il t r t low t hd:sta t hd:dat t f t high t su:dat s s p p t su:sto smbdat smbclk notes: smbus/i 2 c description s = start condition p = stop condition a = acknowledge a = not acknowledge r/w = read enable at high; write enable at low t buf t su:sta figure 27. write byte protocol master to slave slave to master 171181811 s slave address w a command code a data byte ap
isl97671a 18 fn7709.1 march 24, 2011 smbus/i 2 c communications the isl97671a can be controlled by smbus/i 2 c for pwm or dc dimming. the leds driving is default to off and the users will need the smbus/i 2 c interface to enable the driving and controlling of various parameters that will be described in this section. please note that the isl97671a can also be controlled by an external pwm signal for pwm dimming without any smbus/i 2 c interface. to do so, the users need to pull the smbclk and smbdat pins to low or ground the pins permanently if smbus/i 2 c control is not used. the switching frequency is fixed at 600khz if smbus/i 2 c is not used. write byte the write byte protocol is only three bytes long. the first byte starts with the slave address followed by the ?command code,? which translates to the ?register index? being written. the third byte contains the data byte that must be written into the register selected by the ?command code?. a shaded label is used on cycles during which the slaved backlight controll er ?owns? or ?drives? the data line. all other cycles are driven by the ?host master.? read byte figure 28 shows the four byte long read byte protocol starts out with the slave address followed by the ?command code? which translates to the ?register index.? subsequently, the bus direction turns around with the re-broadcast of the slave address with bit 0 indicating a read (?r?) cycle. the fourth byte contains the data being returned by the backlight co ntroller. that byte value in the data byte reflects the value of the register being queried at the ?command code? index. note the bus directions, which are highlighted by the shaded label that is used on cycles during which the slaved backlight controller ?owns? or ?drives? the data line. all other cycles are driven by the ?host master.? slave device address the slave address contains 7 msb plus one lsb as r/w bit, but these 8 bits are usually called slave address bytes. figure 29 shows the high nibble of the slave address byte is 0x5 or 0101b to denote the ?backlight controller class.? bit 3 in the lower nibble of the slave address byte is 1. bit 0 is always the r/w bit, as specified by the smbus/i 2 c protocol. note: in this docu ment, the device address will always be expressed as a full 8-bit address instead of the shorter 7-bit address typically used in other backlight controller specifications to avoid confusion. th erefore, if the device is in the write mode where bit 0 is 0, the slave address byte is 0x58 or 01011000b. if the device is in the read mode where bit 0 is 1, the slave address byte is 0x59 or 01011001b. the backlight controller may sense the state of the pins at por or during normal operation - the pins will not change state while the device is in operation. smbus/i 2 c register definitions the backlight controller registers are byte wide and accessible via the smbus/i 2 c read/write byte protocols. their bit assignments are provided in the following sections with reserved bits containing a default value of ?0?. figure 28. read byte protocol master to slave slave to master 1711 8 11811811 s slave address w acommand code as slave address r a data byte a p figure 29. slave address byte definition device identifier device address r e a d / w r i t e b i t msb lsb 0101100r/ w table 3a. isl97671a register listing address register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default value smbus/i 2 c protocol 0x00 pwm brightness control register brt7 brt6 brt5 brt4 brt3 brt2 brt1 brt0 0xff read and write 0x01 device control register reserved reserved reserved reserved reserved pwm_md pwm_sel bl_ctl 0x00 read and write 0x02 fault/status register reserved reserved 2_ch_sd 1_ch_sd bl_stat ov_curr thrm_shdn fault 0x00 read only
isl97671a 19 fn7709.1 march 24, 2011 pwm brightness control register (0x00) the brightness control resolution has 256 steps of pwm duty cycle adjustment. figure 30 shows the bit assignment. all of the bits in this brightness control register can be read or write. step 0 corresponds to the minimum step where the current is less than 10a. steps 1 to 255 represent the linear steps be tween 0.39% and 100% duty cycle with approximat ely 0.39% duty cycle adjustment per step. ? an smbus/i 2 c write byte cycle to register 0x00 sets the pwm brightness level only if the backlight controller is in smbus/i 2 c mode (see table 4) operating modes selected by device control register bits 1 and 2). ? an smbus/i 2 c read byte cycle to register 0x00 returns the programmed pwm brightness level. ? an smbus/i 2 c setting of 0xff for register 0x00 sets the backlight controller to the maximum brightness. ? an smbus/i 2 c setting of 0x00 for register 0x00 sets the backlight controller to the minimum brightness output. ? default value for register 0x00 is 0xff. 0x03 identification register led panel mfg3 mfg2 mfg1 mfg0 rev2 rev1 rev0 0xc8 read only 0x07 dc brightness control register brtdc7 brtdc6 brtdc5 brtdc4 brtdc3 brtdc2 brtdc1 brtdc0 0xff read and write 0x08 configuration register reserved directpwm 0 1 1 fsw reserved vsc 0x1f read and write 0x09 output channel register reserved reserved ch5 ch4 ch3 ch2 ch1 ch0 0x3f read and write 0x0a phase shift deg equal phase phase shift6 phase shift5 phase shift4 phase shift3 phase shift2 phase shift1 phase shift0 0x00 read and write table 3a. isl97671a register listing (continued) address register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default value smbus/i 2 c protocol table 3b. data bit descriptions address register data bit descriptions 0x00 pwm brightness control register brt[7..0] = 256 steps of dpwm duty cycle brightness control 0x01 device control register pwm_md = pwm mode select bi t (1 = absolute brightness, 0 = % change), default = 0 pwm_sel = brightness control select bit (1 = control by pwmi, 0 = control by smbus/i 2 c), default = 0 bl_ctl = bl on/off (1 = on, 0 = off), default = 0 0x02 fault/status register 2_ch_sd = two led output channels are shutdown (1 = shutdown, 0 = ok) 1_ch_sd = one led output channel is shutdown (1 = shutdown, 0 = ok) bl_stat = bl status (1 = bl on, 0 = bl off) ov_curr = input overcurrent (1 = overcurrent condition, 0 = current ok) thrm_shdn = thermal shutdown (1 = thermal fault, 0 = thermal ok) fault = fault occurred (logic ?or? of all of the fault conditions) 0x03 identification register mfg[3..0] = manufacturer id (16 vendors available. intersil is vendor id 9) rev[2..0] = silicon rev (rev 0 through rev 7 allowed for silicon spins) 0x07 dc brightness control register brtdc[7..0 ] = 256 steps of dc brightness control 0x08 configuration register directpwm = forces the pwm input signal to di rectly control the current sources. bits 3, 4, and 5 should be 1, 1, 0 fsw = switching frequencies selection, fsw = 0 = 1.2mhz. fsw = 1 = 600kmhz vsc[0] = short circuit thresholds select ion, 0 = disabled, 1 = 7.2v minimum 0x09 output channel mask/fault readout register ch[5..0] = output channel read and write. in write, 1 = channel enabled, 0 = channel disabled. in read, 1 = channel ok, 0 = channel not ok/channel disabled 0x0a phase shift degree equalphase = controls phase shift mode - when 1, phase shift is 360/n (where n is the number of channels enabled). when 0, phase shift is defined by phaseshift<6:0>. ps[6..0] = 7-bit phase shift setting - phase shift between each channel is phaseshift<6:0>/(255*pwmfreq). in direct pwm modes, phase shift between each channel is phaseshift<6:0>/12.8mhz.
isl97671a 20 fn7709.1 march 24, 2011 device control register (0x01) this register has two bits that control either smbus/i 2 c controlled or external pwm controlled pwm dimming and a single bit that controls the bl on/off state. the remaining bits are reserved. the bit assignment is shown in figure 31. all other bits in the device control register will read as low unless otherwise written. ? all reserved bits have no fu nctional effect when written. ? all defined control bits return their current, latched value when read. a value of 1 written to bl_ctl turn s on the bl in 4ms or less after the write cycle completes. the bl is ? deemed to be on when bit 3 bl_stat of register 0x02 is 1 and register 0x09 is not 0. ? a value of 0 written to bl_ctl immediately turns off the bl. the bl is deemed to be off when bit 3 bl_stat of register 0x02 is 0 and register 0x09 is 0. ? when smbus/i 2 c mode with dpst is selected, register 0x00 reflects the last value written to it from smbus/i 2 c. the default value for register 0x01 is 0x00. the pwm_sel bit determin es whether the smbus/i 2 c or pwm input should drive the output brightness in terms of pwm dimming. when pwm_sel bit is 1, the pwm drives the output brightness regardless of what the pwm_md is. when the pwm_sel bit is 0, the pwm_md bit selects the manner in which the pwm dimming is to be interpreted; when this bit is 1, the pwm dimm ing is based on the smbus/i 2 c brightness setting. when this bit is 0, the pwm dimming reflects a percentage change in the current brightness programmed in the smbus/i 2 c register 0x00, i.e. dpst (display power saving technology) mode as: where: cbt = current brightness setting from smbus/i 2 c register 0x00 without influence from the pwm figure 30. descriptions of brightness control register register 0x00 pwm brig htness control register brt7 brt6 brt5 brt4 brt3 brt2 brt1 brt0 bit 7 (r/w) bit 6 (r/w) bit 5 (r/w) bit 4 (r/w) b it 3 (r/w) bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) bit assignment bit field definitions brt[7..0] = 256 steps of pwm brightness levels figure 31. descriptions of device control register register 0x01 device control register reserved reserved reserved reserved reserved pwm_md pwm_sel bl_ctl bit 7 (r/w) bit 6 (r/w) bit 5 (r/w) bit 4 (r/w) b it 3 (r/w) bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) pwm_md pwm_sel bl_ctl mode xx0backlight off 001smbus/i 2 c and pwm dimming (dpst) 0 1 1 pwmi controlled pwm dimming 101smbus/i 2 c controlled pwm dimming 111smbus/i 2 c controlled pwm dimming table 4. operating modes sele cted by device control register bits 1 and 2 pwm_md pwm_sel mode x 1 pwm mode 10smbus/i 2 c mode 00smbus/i 2 c and pwm mode with dpst dspt brightness cbt pwm = (eq. 16)
isl97671a 21 fn7709.1 march 24, 2011 pwm = is the percent duty cycle of the pwm for example, the cbt = 50% duty cycle programmed in the smbus/i 2 c register 0x00 and the pwm frequency is tuned to be 200hz with an appropriate capacitor at the fpwm pin. on the other hand, pwm is fed with a 1khz 30% high pwm signal. when pwm_sel = 0 and pwm_md = 0, the device is in dpst operation where dpst brightness = 15% pwm dimming at 200hz. fault/status register (0x02) this register has 6 status bits that allow monitoring of the backlight controller?s operating state. bit 0 is a logical ?or? of all fault codes to simplify error detection. not all of the bits in this register are fault related (bit 3 is a simple bl status indicator). the remaining bits are reserved and return a ?0? when re ad and ignore the bit value when written. all of the bits in this register are read-only, with the exception of bit 0, which can be cleared by writing to it. ? a read byte cycle to register 0x02 indicates the current bl on/off status in bl_stat (1 if the bl is on, 0 if the bl is off). ? a read byte cycles to register 0x2 also returns fault as the logical or of thrm_shdn, ov_curr, 2_ch_sd, and 1_ch_sd should these events occur. ? 1_ch_sd returns a 1 if one or more channels have faulted out. ? 2_ch_sd returns a 1 if two or more channels have faulted out. ? a fault will not be reported in the event that the bl is commanded on and then imme diately off by the system. ? when fault is set to 1, it will remain at 1 even if the signal which sets it goes away. fault will be cleared when the register 0x02 fault/status register reserved reserved 2_ch_sd 1_ch_sd bl_stat ov_curr thrm_shdn fault bit 7 (r) bit 6 (r) bit 5 (r) bit 4 (r) b it 3 (r) bit 2 (r) bit 1 (r) bit 0 (r) bit bit assignment bi t field definitions bit 5 2_ch_sd = two led output channels are shutdown (1 = shutdown, 0 = ok) bit 4 1_ch_sd = one led output channel is shutdown (1 = shutdown, 0 = ok) bit 3 bl_stat = bl status (1 = bl on, 0 = bl off) bit 2 ov_curr = input overcurrent (1 = overcurrent condition, 0 = current ok) bit 1 thrm_shdn = thermal shutdown (1 = thermal fault, 0 = thermal ok) bit 0 fault = fault occurred (logic ?or? of all of the fault conditions) figure 32. descriptions of fault/status register register 0x03 id register led panel mfg3 mfg2 mfg1 mfg0 rev2 rev1 rev0 bit 7 = 1 bit 6 (r) bit 5 (r) bit 4 (r) bit 3 (r) bit 2 (r) bit 1 (r) bit 0 (r) bit assignment bit field definitions mfg[3..0] = manufacturer id. see ?identification register (0x03)? on page 21. data 0 to 8 in decimal correspond to other vendors data 9 in decimal represents intersil id data 10 to 14 in decimal are reserved data 15 in decimal manufacturer id is not implemented rev[2..0] = silicon rev (rev 0 through rev 7 allowed for silicon spins) figure 33. descriptions of id register
isl97671a 22 fn7709.1 march 24, 2011 dc brightness control register (0x07) the dc brightness control register 0x07 allows users to have additional dimming flexibility by: 1. effectively achieving 16-bits of dimming control when dc dimming is combined with pwm dimming 2. achieving visual or audio noise free 8-bit dc dimming over potentially noisy pwm dimming. the bit assignment is shown in fi gure 34. all of the bits in this register can be read or write. steps 0 to 255 represent the linear steps of current adjustment in dc on-the-fly. it can also be considered as the peak current factory calibration feature to account for various led production batch variations, but external eeprom settings storing an d restoring are required. ? an smbus/i 2 c write byte cycle to register 0x07 sets the brightness level in dc only. ? an smbus/i 2 c read byte cycle to register 0x07 returns the current dc brightness level. ? default value for register 0x07 is 0xff. configuration register (0x08) the configuration register provides many extra functions that users can explore in order to optimize the driver performance at a given application. a directpwm bit allows direct pwm where the output current follows the same input pwm signal.the fsw bit allows users to set the boost conversion switching frequency between 1.2mhz and 600khz. the vsc bits allow users to set led string short circuit threshold vsc to 7.2v or disable it. the bit assignment is shown in figure 35. the default value for register 0x08 is 0x1f. figure 34. descriptions of dc brightness control register register 0x07 dc brightness control register brtdc7 brtdc6 brtdc5 brtdc4 brtdc3 brtdc2 brtdc1 brtdc0 bit 7 (r/w) bit 6 (r/w) bit 5 (r/w) bit 4 (r/w) b it 3 (r/w) bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) bit assignment bit field definitions brtdc[7..0] = 256 steps of dc brightness levels
isl97671a 23 fn7709.1 march 24, 2011 output channel mask/fault readout register (0x09) this register can be read or write; the bit position corresponds to the channel. for example, bit 0 corresponds to ch0 and bit 5corresponds to ch5 and so on. wr iting data to this register, it enables the channels of interest. when reading data from this register, any disabled channel an d any faulted out channel will read as 0. this allows the user to determine which channel is faulty and optionally not enabling it in order to allow the rest of the system to continue to func tion. additionally, a faulted out channel can be disabled and re-enabled in order to allow a retry for any faulty channel without having to power-down the other channels. the bit assignment is shown in figure 36. the default for register 0x09 is 0x3f. register 0x08 configuration register reserved reserved bit5 bi t4 bit3 fsw reserved vsc bit 7 (r/w) bit 6 (r/w) 0 (w) 1(w) 1(w) b it 2 (r/w) bit 1 (r/w) bit 0 (r/w) bit assignment bit field definitions directpwm forces the pwmi signal to directly co ntrol the current sources. note that there is some synchronous delay between pwmi and current sources. bits[5-3] these bits should always be written as 011 fsw 2 levels of switching freque ncies (1 = 1,200khz, 0 = 600khz) vsc[0] 2 levels of short-circuit thresholds (0 = disabled, 1 = 7.5v minimum) figure 35. descriptions of configuration register figure 36. output channel register register 0x09 output channel register reserved reserved ch5 ch4 ch3 ch2 ch1 ch0 bit 7 (r/w) bit 6 (r/w) bit 5 (r /w) bit 4 (r/w) bit 3 (r/w) bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) bit assignment bit field definitions ch[5..0] ch5 = channel 5, ch4 = channel 4 and so on
isl97671a 24 fn7709.1 march 24, 2011 phase shift control register (0x0a) the phase shift control register is used to set phase delay between each channels. when bit 7 is set high, the phase delay is set by the number of channels enabled and the pwm frequency. refer to figures 3 and 4, the delay time is defined by equation 17: where n is the number of channels enabled, and t fpwm is the period of the pwm cycle. when bit 7 is set low, the phase delay is set by bits 6 to 0 and the pwm frequency. referencing figure 24, the programmable delay time is defined by equation 18: where ps is an integer from 0 to 127, and t fpwm is the period of the pwm cycle. by default, all the register bits are set low, which sets zero delay between each cha nnel. note that the user should not program the register to give more than one period of the pwm cycle delay between the first and last enabled channels. components selections according to the inductor voltag e-second balance principle, the change of inductor current during the switching regulator on time is equal to the change of inductor current during the switching regulator off time. since the voltage across an inductor is: and i l at on = i l at off, therefore: where d is the switching duty cycle defined by the turn-on time over the switching period. v d is schottky diode forward voltage that can be neglected for approximation. rearranging the terms without accounting for v d gives the boost ratio and duty cycle respectively as: input capacitor switching regulators require input capacitors to deliver peak charging current and to reduce the impedance of the input supply. this reduces interaction between the regulator and input supply, thereby improving system stability. the high switching frequency of the loop causes almost all ripple current to flow in the input capacitor, which must be rated accordingly. a capacitor with low internal series resistance should be chosen to minimize heating effects and improve system efficiency, such as x5r or x7r ceramic capacitors , which offer small size and a lower value of temperature and voltage coefficient compared to other ceramic capacitors. in boost mode, input current flows continuously into the inductor; ac ripple component is only proportional to the rate of the inductor charging, thus, smaller value input capacitors may be used. it is recommended that an input capacitor of at least 10f be used. ensure the voltage rating of the input capacitor is suitable to handle the full supply range. figure 37. descriptions of phase shift control register register 0x0a phase shift control register equalphase phaseshift6 phaseshift5 phaseshift4 p haseshift3 phaseshift2 phaseshift1 phaseshift0 bit 7 (r/w) bit 6 (r/w) bit 5 (r/w) bit 4 (r/w) b it 3 (r/w) bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) bit assignment bit field definitions equalphase controls phase shift mode - when 0, phase sh ift is defined by phaseshift<6:0>. when 1, phase shift is 360/n (where n is the number of channels enabled). phaseshift[6..0] 7-bit phase shift setti ng - phase shift between each channel is phaseshift<6:0>/(255*pwmfreq) in direct pwm modes, phase shift between each channel is phaseshift<6:0>/12.8mhz t d1 t fpwm n ? () = (eq. 17) t pd ps 6 0 xt > , < fpwm 255 () ? () = (eq. 18) v l l i l t ? = (eq. 19) v ( i 0 ) l ? dt s v o v d v i ? ? () = l1 ( d ) t s ? ? ? (eq. 20) v o v i 11d ? () ? = ? (eq. 21) dv o ( v i ) v o ? ? = (eq. 22)
isl97671a 25 fn7709.1 march 24, 2011 inductor the selection of the inductor should be based on its maximum current (i sat ) characteristics, power dissipation (dcr), emi susceptibility (shielded vs unshielded), and size. inductor type and value influence many key parameters, including ripple current, current limit, efficiency, transient performance and stability. the inductor?s maximum current capability must be adequate enough to handle the peak current at the worst case condition. if an inductor core is chosen with too low a current rating, saturation in the core will cause the effective inductor value to fall, leading to an increase in peak to average current level, poor efficiency and overheating in the core. the series resistance, dcr, within the inductor causes conduction loss and heat dissipation. a shielded inductor is usually more suitable for emi susceptible applications, such as led backlighting. the peak current can be derived from the voltage across the inductor during the off period, as expressed in equation 23: the choice of 85% is just an average term for the efficiency approximation. the first term is the average current, which is inversely proportional to the input voltage. the second term is the inductor current change, which is inversely proportional to l and f sw . as a result, for a given switching frequency and minimum input voltage on which the system operates, the inductor i sat must be chosen carefully. at a given inductor size, usually the larger the inductance, the higher the series resistance because of the extra winding of the coil. thus, the higher the inductance, the lower the peak cu rrent capability. the isl97671a current limit should also have to be taken into account. output capacitors the output capacitor acts to smooth the output voltage and supplies load current directly duri ng the conduction phase of the power switch. output ripple voltage consists of the discharge of the output capacitor for i lpeak during fet on and the voltage drop due to flowing through the esr of the output capacitor. the ripple voltage can be shown as: the conservation of charge princi ple in equation 24 also brings up the fact that during the boos t switch off period, the output capacitor is charged with the inductor ripple current minus a relatively small output current in boost topology. as a result, the user needs to select an output capacitor with low esr and enough input ripple current capability. output ripple v co , can be reduced by increasing co or f sw , or using small esr capacitors. in general, ceramic capacitors are the best choice for output capacitors in small to medium sized lcd backlight applications due to their cost, form factor, and low esr. a larger output capacitor will also ease the driver response during pwm dimming off period due to the longer sample and hold effect of the output drooping. the driver does not need to boost harder in the next on pe riod that mini mizes transient current. the output capacitor is also needed for compensation, and, in general 2x4.7f/50v ceramic capacitors are suitable for notebook display backlight applications. schottky diode a high speed rectifier diode is necessary to prevent excessive voltage overshoot, especially in the boost configuration. low forward voltage and reverse le akage current will minimize losses, making schottky diodes the preferred choice. although the schottky diode turns on only during the boost switch off period, it carries the same peak current as the inductor, and therefore, a suitable current rated schottky diode must be used. applications high current applications each channel of the isl97671a can support up to 50ma. for applications that need higher cu rrent, multiple channels can be grouped to achieve the desirable current. for example, the cathode of the last led can be connected to ch0 to ch2, this configuration can be treated as a single string with 150ma current driving capability. multiple drivers operation for large lcd panels where more than 6channels of leds are needed, multiple isl97671as with each driver having its own supporting components can be controlled together with the common smbus/i 2 c. while the isl97671a does not have extra pins strappable slave address feature, but a separate en signal can be applied to each driver for asynchronous operation. a trade-off of such scheme is that an exact faulty channel cannot be identified since both controllers have the same i 2 c slave address. il pk v o ( i o ) 85% ( v i ) 12v i v o ( v i ) l ( v o f sw ) ? ? [] ? + ? = (eq. 23) v co i ( o c o df s ) i ( o esr () + ? ? = (eq. 24) figure 38. ganging multiple channels for high current applications ch0 ch1 ch2 v out
isl97671a 26 fn7709.1 march 24, 2011 low voltage operations the isl97671a vin pin can be seperately biased from the leds power input to allow low voltage operation. for systems that have only single supply, v out can be tied to the driver vin pin to allow initial start-up, (see figure 40). the circuit works as follows; when the input voltage is available and the device is not enable, the v out follows v in with a schottky diode voltage drop. the v out bootstrapped to vin pin allows an initial startup once the part is enable. once the driver starts up with v out regulating to the target, the vin pin voltage also increases. as long as the v out does not exceed 26.5v and the extra power loss on v in is acceptable, this configuration ca n be used for input voltage as low as 3.0v. the fault protection fet feature cannot be used in this configuration. for systems that have dual supplie s, vin pin can be biased from 5v to 12v while input voltage can be as low as 2.7v, (see figure 41). in this configuration v bias is greater than or equal to v in for using the fault fet. 16-bit dimming the smbus/i 2 c controlled pwm and dc dimmings can be combined to effectively provide 16 bits of dimming capability, which can be valuable for automotive and avionics display applications. rgb leds or field sequenctial led backlighting the isl97671a allows users to select the six channels of pwm dimming currents in any sequences and combinations that rgb leds or field sequential backlighting applications can be considered. on the other hand, the channel currents cannot be dimmed independently at the same time. for example, an rgb leds applic ation requires channels 0 and 1 for the red leds at 40ma peak with 25% dimming, channels 2 and 3 for green leds at 20ma peak with 50% dimming, and channels 4 and 5 for blue le ds at 10ma peak with 100% dimming. first the i led is set at 40ma with an appropriate r set , then the smbus/i 2 c programming sequences are shown in the followings: register0x01 data 0x05 ?turn bl on and select smbus dimming? register0x09 data 0x03 ?select ch 0 and 1? register0x07 data 0xff ?set 100% of 40ma in dc? register0x00 data 0x40 ?apply 25% pwm dimming? register0x09 data 0x0c ?select ch 2 and 3? register0x07 data 0x80 ?set 50% of 40ma in dc? register0x00 data 0x80 ?apply 50% pwm dimming? register0x09 data 0x30 ?select ch 4 and 5? register0x07 data 0xff ?set 100% of 40ma in dc? register0x00 data 0xff ?apply 100% pwm dimming? figure 39. multiple drivers operation smbclk smbdat en smbclk smbdat en smbclk smbdat en figure 40. single supply 3v operation vin = 3v~21v smbdat/sda pwm comp vin ovp rset vdc smbclk/scl ch0 ch3 ch2 ch4 ch5 fpwm 2 4 7 6 5 17 8 15 14 13 12 11 10 16 18 lx 20 pgnd 19 agnd 9 isl97671a ch1 en 3 26.5v, 6 x 50ma* fault 1 *vin >12v figure 41. dual supplies 2.7v operation vin = 2.7~26.5v 45v, 6 x 50ma* *vin > 12v smbdat/sda pwm comp vin ovp rset vdc smbclk/scl ch0 ch3 ch2 ch4 ch5 fpwm 2 4 7 6 5 17 8 15 14 13 12 11 10 16 18 lx 20 pgnd 19 agnd 9 isl97671a ch1 en 3 vbias = 5v~12v fault 1 q1 (optional)
isl97671a 27 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7709.1 march 24, 2011 for additional products, see www.intersil.com/product_tree compensation the isl97671a has two main elements in the system; the current mode boost regulator and the op amp based multi-channel current sources. the isl97671a incorporates a transconductance amplifier in its feedback path to allow the user some levels of adjustment on th e transient response and better regulation. the isl97671a uses current mode control architecture, which has a fast current sense loop and a slow voltage feedback loop. the fast current feedback loop does not require any compensation. the slow voltage loop must be compensated for stable operation. the compensation network is a series rc, cc1 network from comp pin to ground and an optional cc2 capacitor connected to the comp pin. the rc sets the high frequency integrator gain for fast transient response and the cc1 sets the integrator zero to ensure loop stability. for most applications, rc is in the range of 15k ? and cc1 is in the range of 2.2nf. depends on the pcb layout, a cc2, in range of 47pf, may be needed to create a pole to cancel the output capacitor esr?s zero effect for stability. products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl97671a to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 3/24/11 fn7709.1 initial release to web.
isl97671a 28 fn7709.1 march 24, 2011 package outline drawing l20.3x4 20 lead quad flat no-lead plastic package rev 1, 3/10 typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 0.10 m c a b mc 0.05 0.15 0.08 c 0.10 c a b c c 4.00 3.00 20x 0.400.10 2.65 1.65 0.25 0.50 (2.80) (1.65) +0.10 -0.15 +0.10 -0.15 +0.05 -0.07 20x a a 4 (4x) seating plane 0.9 0.10 5 0.2 ref 0.05 max. see detail "x" 0.00 min. (c 0.40) 1 20 17 16 11 6 10 7 (3.80) (2.65) (20 x 0.25) (20 x 0.60) (16 x 0.50) 16x view "a-a" pin 1 index area pin 1 index area 6 6

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